1. Field of the Invention
The invention relates to a thin film transistor (TFT) and a method of producing the same, and also to a semiconductor circuit having a plurality of thin film transistors (TFTs) and a method of producing the same. A thin film transistor produced in accordance with the invention may be formed on either of an insulating substrate such as glass, and a semiconductor substrate such as single crystal silicon. Particularly, the invention relates a semiconductor circuit comprising a matrix circuit which operates at a low speed, such as a monolithic active matrix circuit (which may be used in a liquid crystal display or the like), and a peripheral circuit which drives the active matrix circuit and operates at a high speed. The invention relates also to a thin film transistor which is produced by crystallization and activation according to thermal annealing.
2. Description of the Prior Art
Recently, researches are conducted on insulated gate semiconductor devices having a thin film active layer (also referred to as an active region). Particularly, thin film insulated gate semiconductor devices, or so-called thin film transistors (TFTs) are vigorously studied. Such thin film transistors are formed on a transparent insulating substrate so as to be used for controlling pixels or in a driver circuit in a liquid crystal display device, etc. having a matrix structure. Thin film transistors are classified into amorphous silicon TFTs and crystalline silicon TFTs, depending on the kind and crystal state of a used semiconductor material.
A semiconductor of an amorphous state has generally a low electric field mobility, and therefore cannot be used in a TFT which must operate at a high speed. Since P-type amorphous silicon has a very low electric field mobility, moreover, it is impossible to produce a P-channel TFT (PMOS TFT). Consequently, it is impossible to produce a complementary MOS circuit (CMOS) which consists of combinations of a P-channel TFT and an N-channel TFT (NMOS TFT).
In contrast, a crystalline semiconductor has a higher electric field mobility than that of an amorphous semiconductor, and therefore can operate at a high speed. When using crystalline silicon, since not only an NMOS TFT but also a PMOS TFT can be produced in the same manner, it is possible to produce a CMOS circuit. For example, a known liquid crystal display device of the active matrix type has a so-called monolithic structure in which not only the active matrix region but also a peripheral circuit (including a driver circuit, etc.) are constructed by CMOS crystalline TFTs. From these reasons, researches and developments on TFTs using crystalline silicon are vigorously conducted.
In an example of a method of obtaining crystalline silicon, amorphous silicon is crystallized by irradiating it with a laser or intense light equivalent to a laser. Because of instability of the laser output and instability due to a very short process period, however, this method offers no prospect for mass production or practical use.
Now, a method which may be practically employed is the one in which amorphous silicon is thermally crystallized. According to this method, it is possible to obtain crystalline silicon with reduced variation between batches. However, this method has a problem.
Generally, the formation of crystalline silicon requires annealing of a long period and at about 600.degree. C., or annealing at a high temperature of 1,000.degree. C. or higher. In the case where the latter method is employed, a selectable substrate is limited to one made of quartz, resulting in that the cost of a substrate is very high. In the case where the former method is employed, a substrate can be selected from a wide range, but there arises another problem.
When an inexpensive alkalifree glass substrate (for example, No. 7059 produced by Corning Co. Ltd.) is used, a conventional process of producing a TFT is roughly conducted in the following manner:
(1) formation of an amorphous silicon film; PA1 (2) crystallization of the amorphous silicon film (600.degree. C. or higher, and 24 hours or longer); PA1 (3) formation of a gate insulating film; PA1 (4) formation of a gate electrode; PA1 (5) Introduction of doping impurities (by the ion implantation method or ion doping method); PA1 (6) activation of the doping impurities (600.degree. C. or higher, and 24 hours or longer); PA1 (7) formation of a layer insulator; and PA1 (8) formation of source and drain electrodes. PA1 1) Deposition of an amorphous silicon film PA1 1') Introduction of a catalytic element (by an ion injection or an ion doping method) PA1 2) Crystallization of amorphous silicon film (at 600.degree. C or less, within 8 hours) PA1 3) Deposition of a gate insulating film PA1 4) Formation of a gate electrode PA1 5) Introduction of doping impurities (by an ion injection or an ion doping method) PA1 5') Deposition of a material having catalytic element to a silicon film PA1 6) Activation of a doping impurity (600.degree. C. or less, within 8 hours) PA1 7) Formation of interlayer insulator PA1 8) Formation of source, drain electrode or, PA1 1) Deposition of an amorphous silicon film PA1 1') Introduction of a catalytic element (by an ion injection or an ion doping method) PA1 2) Crystallization of an amorphous silicon film (600.degree. C. or less, within 8 hours) PA1 3) Deposition of a gate insulating film PA1 4) Formation of a gate electrode PA1 5) Introduction of a doping impurity (by an ion injection or an ion doping method) PA1 5') Introduction of a catalytic element (by ion injection or an ion doping method) PA1 6) Activation of a doping impurity (600.degree. C. or less, within 8 hours) PA1 7) Formation of an interlayer insulator PA1 8) Formation of source, drain electrode
In the process, steps (2) and (8) have problems. Many kinds of alkalifree glass have a distortion temperature of about 600.degree. C. (593.degree. C. in the case of Corning 7059). Therefore, a process at such a temperature causes problems such as a shrinkage and bend of a substrate. In step (2) which is a first annealing process, a shrinkage of a substrate does not cause a serious problem because a patterning process has not yet been conducted. In step (6), however, a patterning process has been conducted already. When the substrate shrinks in step (6), therefore, the mask alignment in the following steps cannot be properly conducted, thereby forming a major cause for impairing the yield. Consequently, it is desired to conduct the process of step (2) at a temperature lower than the distortion temperature of the substrate, and to conduct the process of step (6) at a further lower temperature (preferably, at a temperature lower than the distortion temperature of glass by 50.degree. C. or lower, and, more preferably, at a temperature lower than the maximum process temperature of step (2) by 50.degree. C or lower).
In order to meet the requirements, a method in which a laser or the like is used as described above may be employed. In addition to the problem of instability of a laser output, however, it was observed there arises another problem in that a stress is generated owing to a difference in temperature rise between the portion to which a laser beam is irradiated (the source and drain regions) and that to which a laser beam is not irradiated (the active region, i.e., the region below the gate electrode), thereby impairing the reliability.
On the other hand, a TFT made of an amorphous semiconductor has a feature that the OFF current is low. Therefore, such a TFT is employed in a use such as a transistor for a pixel circuit of an active matrix of a liquid crystal display device which does not require a very high operation speed, in which only a single conductivity type is sufficient, and which requires a TFT having a high ability of retaining charges. However, such a TFT cannot be employed in a peripheral circuit which must operate at a high speed.
In a crystalline silicon TFT, a leak current flowing when no voltage is applied to the gate (i.e., during the nonselected period) is larger than that in an amorphous silicon TFT. When a crystalline silicon TFT is to be used in a liquid crystal display device, measures that an auxiliary capacitor for compensating the leak current is disposed, and that two TFTs are connected in series are taken so as to reduce the leak current.
FIG. 5 shows a block diagram of an active matrix circuit used in a liquid crystal display device. As peripheral circuits, a column decoder 101 and a row decoder 102 are disposed on a substrate 107. Pixel circuits 104 each consisting of a transistor and a capacitor are formed in a matrix region 103. The matrix region and the peripheral circuits are connected to each other through wirings 105 and 106. TFTs used in the peripheral circuits are required to have a property of a high speed, and TFTs used in the pixel circuits are required to have a property of a low leak current. Although these properties are physically contradictory to each other, it is required to form the both kinds of TFTs on the same substrate and by the same process.
Generally, the formation of crystalline silicon requires annealing of a long period and at about 600.degree. C., or annealing at a high temperature of 1,000.degree. C. or higher. For example, it is impossible to construct a structure in which a high OFF resistance of amorphous silicon TFTs is utilized and these TFTs and a peripheral circuit consisting of polysilicon TFTs which have a high mobility are formed on the same substrate, because amorphous silicon is crystallized in the above-mentioned annealing process.